借用zqadam的逻辑改的：

`define S1 0

`define S2 1

`define S3 2

`define S4 3

`define S5 4

`define S6 5

`define S7 6

`define S8 7

module clk_gen2 (clk,reset,clk1,clk2,clk4,fetch,alu_clk);

input clk,reset;

output clk1,clk2,clk4,fetch,alu_clk;

wire clk,reset;

reg clk2,clk4,fetch,alu_clk;

reg[7:0] state,next_state;

wire s_s1 = state[`S1];

wire s_s2 = state[`S2];

wire s_s3 = state[`S3];

wire s_s4 = state[`S4];

wire s_s5 = state[`S5];

wire s_s6 = state[`S6];

wire s_s7 = state[`S7];

wire s_s8 = state[`S8];

assign clk1 = ~clk;

//----------------------状态机-----------------

//状态机的时序逻辑

always @(negedge clk)

state <= next_state;

//状态机的组合逻辑（可能没有实际的组合电路），仅表示状态跳转，

//增强代码的可读性

//既然是时钟发生器，最好不要用reset，否则复位将导致时钟中断，

//特别时钟要输出给其它模块或其它游器件用的时候

always @(state)

begin

next_state = 8'b0000_0000;

case(1'b1)

state[`S1] : next_state[`S2] = 1'b1;

state[`S2] : next_state[`S3] = 1'b1;

state[`S3] : next_state[`S4] = 1'b1;

state[`S4] : next_state[`S5] = 1'b1;

state[`S5] : next_state[`S6] = 1'b1;

state[`S6] : next_state[`S7] = 1'b1;

state[`S7] : next_state[`S8] = 1'b1;

state[`S8] : next_state[`S1] = 1'b1;

default : next_state[`S1] = 1'b1;

endcase

end

//-----------------处理逻辑-------------------------

always @(negedge clk)

clk2 <= ~clk2;

always @(negedge clk)

if (s_s1 | s_s2)

alu_clk <= ~alu_clk;

always @(negedge clk)

if (s_s2 | s_s4 | s_s6 | s_s8)

clk4 <= ~clk4;

always @(negedge clk)

if (s_s4 | s_s8)

fetch <= ~fetch;

endmodule