奇数次分频器

module count(out,clk,clr);

parameter N=5;

output out;

input clk,clr;

reg out1,out2;

reg [N/2:0] count1,count2;

always @(posedge clk or posedge clr )

if(clr) begin

count1=0;

out1=0;

end

elsebegin

count1 = count1 + 1;

if( count1 == ((N+1)/2))

out1 =!out1;

else if (count1==N)

begin

out1=~out1;

count1=0;

end

end

always @(negedge clk or posedge clr )

if(clr) begin

count2=0;

out2=0;

end

elsebegin

count2 = count2 + 1;

if( count2 == (N+1)/2 )

out2 =!out2;

else if (count2==N)

begin

out2=~out2;

count2=0;

end

end

assign out=out1|out2;

endmodule

可以在其他程序中调用,例如七分频 ：

......

count #(7) counter(out,clk,clr);

......