可综合的Verilog
FIFO存储器 This example describes a synthesizable implementation of a
FIFO. The
FIFO depth and
FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the
FIFO depth is 4 and the
FIFO width is 32 bits. The input/output p ..
[
查看全文]