-----------------------------------------------------------------------------

--

--The following information has been generated by Exemplar Logic and

--may be freely distributed and modified.

--

--Design name : pseudorandom

--

--Purpose : This design is a pseudorandom number generator. This design

--will generate an 8-bit random number using the polynomial p(x) = x + 1.

--This system has a seed generator and will generate 2**8 - 1 unique

--vectors in pseudorandom order. These vectors are stored in a ram which

--samples the random number every 32 clock cycles. This variance of a

--priority encoded seed plus a fixed sampling frequency provides a truely

--random number.

--

--This design used VHDL-1993 methods for coding VHDL.

--

----------------------------------------------------------------------------

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity divide_by_n is

generic (data_width: natural := 8 );

port (

data_in: inUNSIGNED(data_width - 1 downto 0) ;

load: instd_logic ;

clk: instd_logic ;

reset: instd_logic ;

divide: out std_logic

);

end divide_by_n ;

architecture rtl of divide_by_n is

signal count_reg : UNSIGNED(data_width - 1 downto 0) ;

constant max_count : UNSIGNED(data_width - 1 downto 0) := (others => '1') ;

begin

cont_it :process(clk,reset)

begin

if (reset = '1') then

count_reg <= (others => '0') ;

elsif (clk = '1' and clk'event) then

if (load = '1') then

count_reg <= data_in ;

else

count_reg <=count_reg + "01" ;

end if ;

end if;

end process ;

divide <= '1' when count_reg = max_count else '0' ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity dlatrg is

generic (data_width: natural := 16 );

port (

data_in: inUNSIGNED(data_width - 1 downto 0) ;

clk: instd_logic ;

reset: instd_logic ;

data_out : out UNSIGNED(data_width - 1 downto 0)

);

end dlatrg ;

architecture rtl of dlatrg is

begin

latch_it : process(data_in,clk,reset)

begin

if (reset = '1') then

data_out <= (others => '0') ;

elsif (clk = '1') then

data_out <= data_in ;

end if;

end process ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity lfsr is

generic (data_width: natural := 8 );

port (

clk: instd_logic ;

reset: instd_logic ;

data_out : out UNSIGNED(data_width - 1 downto 0)

);

end lfsr ;

architecture rtl of lfsr is

signal feedback : std_logic ;

signal lfsr_reg : UNSIGNED(data_width - 1 downto 0) ;

begin

feedback <= lfsr_reg(7) xor lfsr_reg(0) ;

latch_it :process(clk,reset)

begin

if (reset = '1') then

lfsr_reg <= (others => '0') ;

elsif (clk = '1' and clk'event) then

lfsr_reg <= lfsr_reg(lfsr_reg'high - 1 downto 0) & feedback ;

end if;

end process ;

data_out <= lfsr_reg ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity priority_encoder is

generic (data_width: natural := 25 ;

address_width : natural := 5 ) ;

port (

data: inUNSIGNED(data_width - 1 downto 0) ;

address : out UNSIGNED(address_width - 1 downto 0) ;

none: out STD_LOGIC

);

end priority_encoder ;

architecture rtl of priority_encoder is

attribute SYNTHESIS_RETURN : STRING ;

FUNCTION to_stdlogic (arg1:BOOLEAN)RETURN STD_LOGIC IS

BEGIN

IF(arg1) THEN

RETURN('1') ;

ELSE

RETURN('0') ;

END IF ;

END ;

function to_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is

variable result: UNSIGNED(SIZE-1 downto 0);

variable temp: integer;

attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;

begin

temp := ARG;

for i in 0 to SIZE-1 loop

if (temp mod 2) = 1 then

result(i) := '1';

else

result(i) := '0';

end if;

if temp > 0 then

temp := temp / 2;

else

temp := (temp - 1) / 2;

end if;

end loop;

return result;

end;

constant zero : UNSIGNED(data_width downto 1) := (others => '0') ;

begin

PRIO :process(data)

variable temp_address : UNSIGNED(address_width - 1 downto 0) ;

begin

temp_address := (others => '0') ;

for i in data_width - 1 downto 0 loop

if (data(i) = '1') then

temp_address := to_unsigned(i,address_width) ;

exit ;

end if ;

end loop ;

address <= temp_address ;

none <= to_stdlogic(data = zero) ;

end process ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

use IEEE.std_logic_unsigned.all ;

entity ram is

generic (data_width: natural := 8 ;

address_width: natural := 8);

port (

data_in: inUNSIGNED(data_width - 1 downto 0) ;

address: inUNSIGNED(address_width - 1 downto 0) ;

we: instd_logic ;

clk: in std_logic;

data_out : out UNSIGNED(data_width - 1 downto 0)

);

end ram ;

architecture rtl of ram is

type mem_type is array (2**address_width downto 0) of UNSIGNED(data_width - 1 downto 0) ;

signal mem : mem_type ;

signal addr_reg : unsigned (address_width -1 downto 0);

begin

data_out <= mem(conv_integer(addr_reg)) ;

I0 : process

begin

wait until clk'event and clk = '1';

if (we = '1') then

mem(conv_integer(address)) <= data_in ;

end if ;

addr_reg <= address;

end process ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity tbuf is

generic (data_width: natural := 16 );

port (

data_in: inUNSIGNED(data_width - 1 downto 0) ;

en: instd_logic ;

data_out : out UNSIGNED(data_width - 1 downto 0)

);

end tbuf ;

architecture rtl of tbuf is

begin

three_state :process(data_in,en)

begin

if (en = '1') then

data_out <=data_in ;

else

data_out <= (others => 'Z') ;

end if;

end process ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity pseudorandom is

generic (data_width: natural := 8 );

port (

seed: inUNSIGNED (24 downto 0) ;

init: inUNSIGNED (4 downto 0) ;

load: instd_logic ;

clk: instd_logic ;

reset: instd_logic ;

read: instd_logic ;

write: instd_logic ;

rand: out UNSIGNED (7 downto 0) ;

none: out std_logic

);

end pseudorandom ;

architecture rtl of pseudorandom is

signal latch_seed : UNSIGNED(24 downto 0) ;

signal encoder_address : UNSIGNED(4 downto 0) ;

signal random_data : UNSIGNED(7 downto 0) ;

signal write_enable : std_logic ;

signal ram_data : UNSIGNED(7 downto 0) ;

begin

I0 : entity work.dlatrg(rtl)

generic map (25)

port map (seed,read,reset,latch_seed) ;

I1 : entity work.priority_encoder(rtl)

generic map (25,5)

port map (latch_seed,encoder_address,none) ;

I2 : entity work.ram(rtl)

generic map (8,5)

port map (random_data,encoder_address,write_enable,clk,ram_data) ;

I3 : entity work.tbuf(rtl)

generic map (8)

port map (ram_data,write,rand) ;

I4 : entity work.lfsr(rtl)

generic map (8)

port map (clk,reset,random_data) ;

I5 : entity work.divide_by_n(rtl)

generic map (5)

port map (init,load,clk,reset,write_enable) ;

end rtl ;